1. Field of the Invention
The present invention relates to a variable length coding apparatus which variable-length-codes the audio, image, data, and other information signals and generates coded arrays and a variable length decoding apparatus which decodes variable length coded arrays.
2. Description of the Related Art
Variable length coding is an encoding system to compress the information content by assigning a short code to the information of high occurrence probability and a long code to the information of low occurrence probability by the use of statistical properties which audio, image, data, and other information signals posses when these information signals are encoded.
In case of the image, for example, the differences of adjacent pixels are concentrated to the vicinity of zero because the correlation between adjacent pixels is high. Therefore, assigning a pixel whose absolute value of the difference is small to a short code and that of large absolute value to a long code enables the compression of the information content. In case of the binary image such as facsimile data, encoding the white length and the black length (run-length coding) and assigning the run length with higher occurrence probability to a short code and that with lower occurrence probability to a long code enables the compression of the information content.
The variable length coding apparatus which carries out coding with the code length made variable generally has a variable length ROM (read-only memory) which stores in advance a variable length code table listing the encoded information signal with correspondence to the variable length code, and a word length ROM, a shift register, and a word length counter.
According to this type of conventional apparatus, information signals comprising n-bit digital data are inputted to the first input terminal, while load pulses are inputted to the second input terminal. The information data is converted to the variable length code and k-bit word length data by the variable length ROM and the word length ROM, and loaded into the shift register and the word length counter, respectively, by the load pulse. The word length counter counts down with the digital value of the loaded word length data designate as an initial value and stops counting when the contents reduce to zero. During the period between the loading of the word length data to the word length counter and the decrement of the data to zero, the output signal of the output terminal is "L," indicating that the variable length coded data from the shift register will appear at the output terminal during this period.
This conventional variable length coding apparatus has a problem that the output of the ROM requires a large number of bits. For example, if the maximum length of the variable length code is 20 bits and input information signal is the n=8 bit data, the word length counter outputs needs k=5 bits. Therefore, the variable length ROM must have n=8 bit address inputs and 25-bit outputs. As a result, four memories each having 8 bits are required. In addition to the ROM of such a large number of bits, the conventional variable length coding apparatus needs a large shift register and a counter, resulting in a large circuit scale.
On the other hand, the variable length decoding apparatus which decodes the variable length codes generally has a shift register, ROM for storing the variable length codes with correspondence to decoded values, and a word length counter.
According to the conventional decoding apparatus, the variable length coded array is inputted to the first input terminal and the reset pulse is inputted to the second terminal at the first timing of the variable length coded array. The word length counter is reset with the reset pulse via a gate and every time one variable length coded array is inputted to the first input terminal, the word length counter counts up by the clock. The variable length coded array is inputted to the shift register in series and shifted by 1 bit. The k-bit word length data outputted from the word length counter and the shifted variable length coded array are given to provided to the ROM. The ROM stores the variable length code table which lists variable length codes with correspondence to decoded values, and if a coded array with the word length removed from the shift register output is located on the variable length code table, the ROM outputs the decoded value and the coincidence pulse VD of negative logic. The coincidence pulse VD is latched with a latch and outputted from the output terminal. The decoded value outputted from the ROM by the coincidence pulse is latched by a latch and outputted from the output terminal. The coincidence pulse is supplied to the word length counter as well via gate and resets the word length counter.
In this conventional variable length decoding apparatus, a ROM with a large number of bits is required. For example, if the maximum code length of the variable length code is 20 bits and the decoded value (information signal) in n=8 bit data, same as that described before, the output of the word length counter requires k=5 bits, and ROM requires the address input of 20+5=25 bits and the output of 9 bits which is yielded by adding 8 bits of decoded value to 1 bit of the coincidence pulse, requiring a capacity as large as 32M.times.9 bits.
As described above, in the conventional variable length coding and decoding apparatus, the variable length code tables are stored in a ROM and a large storage capacity ROM is needed, creating a problem that the circuit scale is extremely large.